1. Field of the Invention
This invention relates to the field of trim circuits, and particularly to trim circuits for operational amplifiers which employ complementary input pairs to achieve a rail-to-rail common mode input range.
2. Description of the Related Art
Operational amplifiers have an associated parameter, referred to as input offset voltage (Vos), which specifies the op amp""s differential input voltage applied to the amplifier""s input terminals when the output voltage or current is zero. Vos is zero for an ideal amplifier. To reduce Vos, some op amps provide one or more xe2x80x9ctrimxe2x80x9d inputs; applying appropriate currents or voltages to the trim inputs reduces Vos.
One example of an op amp with a trimmable Vos is shown in FIG. 1; this approach is described in U.S. Pat. No. 6,194,962 to Chen. The op amp""s input consists of a first differential transistor pair MN1 and MN2, and a complementary differential transistor pair MP1 and MP2; both input pairs are connected to receive a differential input signal applied to input terminals V+ and Vxe2x88x92. MN1 and MN2 are biased with a tail current source 10 and MP1 and MP2 receive a tail current from a source 12. In responding to the differential input voltage, each input pair produces a differential current that feeds in to a folded cascode stage 14, which produces an output current Iout that varies with the differential currents received from the input pairs. A pair of trim inputs TRIM1 and TRIM2 are connected to respective nodes of the folded cascode stage 14.
In operation, the PMOS input pair (MP1, MP2) is active when the input common mode voltage (Vcm) is low (below a pre-set threshold voltage), and the NMOS input pair is active when Vcm is high (above the pre-set threshold voltage). When a low Vcm is applied to the op amp, a first correction current xcex94I1 is applied to TRIM1 or TRIM2 to reduce Vos to zero. The correction provided by xcex94I1 is given by xcex94I1/gmp, where gmp is the transconductance of PMOS transistors MP1 and MP2; correction current xcex94I1 is applied throughout the entire common mode input range. After xcex94I1 has been set, a high Vcm is applied to the op amp, and a second correction current xcex94I2 is applied to TRIM1 or TRIM2 (with xcex94I1 still applied) to reduce Vos. Thus, for a high Vcm, the correction provided by xcex94I1 and xcex94I2 is given by (xcex94I1+AI2)/gmn, where gmn is the transconductance of NMOS transistors MN1 and MN2, since xcex94I1 is present throughout the entire common mode input range, while xcex94I2 is only present at high Vcm.
This approach has several disadvantages. For example, the trim range for a high Vcm offset has to be larger than the untrimmed offset range, due to the effect of the low Vcm correction current xcex94I1. For example, if the untrimmed offset for both high Vcm and low Vcm has a range of xc2x12.5 mV, the trim range for low Vcm can the be set at xc2x12.5 mV, but the trim range for a high Vcm has to be set at xc2x15 mV. In addition, any supply voltage or Vcm dependent mismatch of xcex94I1 and xcex94I2 leads to a supply/Vcm dependence for the post-trim trim Vos at high Vcm. This approach also places a constraint on the procedure used to calibrate the op amp, requiring that the calibration be done in a prescribed sequence.
An operational amplifier is presented which overcomes the problems noted above.
The present op amp provides independent trimming of Vos for both high and low common mode input voltages. The amplifier includes complementary input pairs, and employs a steering circuit which provides a tail current Itail to one input pair when Vcm is less than a threshold voltage Vth, and provides Itail to the other input pair when Vcm is greater than Vth. The input pairs produces an output current Iout through a load stage; Iout varies with the pairs"" differential output currents. The load stage, which is preferably a folded cascode stage, includes one or more trim inputs which enable Vos to be varied with one or more trim signals applied to the trim inputs. A first trim signal generating circuit provides a first trim signal to a trim input only when Vcm is less Vth, and a second trim signal generating circuit provides a second trim signal to a trim input only when Vcm is greater than Vth. This allows the input offset voltages at high and low Vcm to be adjusted independently, thereby avoiding the problems identified above.
In a preferred embodiment, the steering circuit includes a steering transistor which steers tail current to a PMOS input pair when Vcm is less than a threshold voltage Vth, and to a NMOS input pair via a current mirror circuit when Vcm greater than Vth. A first trim signal generating circuit generates a first trim signal, suitable for trimming Vos at low Vcm (PMOS pair active), by mirroring a fixed bias current to a first digital-to-analog converter (DAC) which produces the first trim signal in response. A second trim signal generating circuit generates a second trim signal suitable for trimming Vos at high Vcm (NMOS pair active) when tail current is steered to the NMOS input pair. A diverting circuit is connected to divert the fixed bias current when tail current is steered to the NMOS input pair, such that the first trim signal is reduced to zero. In this way, the first trim signal can be tailored to trim Vos at low Vcm, the second trim signal trims Vos at high Vcm, and each trim signal can be independently varied without affecting the other.